-----------------------------------------------------------------------------
--- TEST BED                                                                 
---                                                           Up Down Counter
-----------------------------------------------------------------------------
--- File Name:  tb_UpDownCounter.vhd
---
--- Description:
--- This block is the test bed.
--- 
--- Will clock the device. And every now and then will press one of the
--- buttons.
--- 
---
--- Limitations:
--- apart from being basic none.
---
--- Errors:
---  None known.
---
--- Dependancies:
---  None.
---
--- Current Target: M4-32/64
--- Simulator:      Symphony EDA - Sonata
--- Target Builder: Latice ispExpert
---
--- Author: Peter Antoine       Date: 07 Jul 2004
----------------------------------------------------------------------------
---                                         Copyright (c) 2004 Peter Antoine
----------------------------------------------------------------------------
--- Version   Author Date        Changes
--- -------   ------ ----------  -------------------------------------------
--- 0.1       PA     07.07.2004  Initial revision
----------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

entity tb_UpDownCounter is
end entity tb_UpDownCounter;

architecture tb of tb_UpDownCounter is

    component UpDownCounter
        port (  reset   : in std_logic;
                clock   : in std_logic;
                up      : in std_logic;
                down    : in std_logic;
                seg_1   : out std_logic_vector(7 downto 0);
                seg_2   : out std_logic_vector(7 downto 0);
                seg_3   : out std_logic_vector(7 downto 0));
    end component UpDownCounter;

    --- internal signals
    signal clock : std_logic := '0';
    signal up    : std_logic := '1';
    signal down  : std_logic := '1';
    signal reset : std_logic := '1';

    signal  s1,s2,s3 : std_logic_vector(7 downto 0);

begin
    clock <= '1' after 5 ns when (clock = '0') else '0' after 5 ns;

    up <= '0' after 200 ns, '1' after 202 ns;
    down <= '0' after 300 ns, '1' after 303 ns;
    reset <= '0' after 100 ns, '1' after 102 ns, '0' after 400 ns, '1' after 403 ns;

    upc: UpDownCounter port map (reset=>reset,clock=>clock,up=>up,down=>down,seg_1=>s1,seg_2=>s2,seg_3=>s3);

end architecture tb;

--- vi:ai:nocin:ts=4 sw=4