-----------------------------------------------------------------------------
---                                                                  Test Bed
---                                                   Random Number Generator
-----------------------------------------------------------------------------
--- File Name:  tb_randgen.vhd
---
--- Description:
--- This block is the test bed for the Random Number Generator.
--- 
---
--- Limitations:
---  Nonr Known.
---
--- Errors:
---  None known.
---
--- Dependancies:
---  None.
---
--- Current Target: None.
--- Simulator:      Symphony EDA - Sonata
---
--- Author: Peter Antoine       Date: 03 Jul 2004
----------------------------------------------------------------------------
---                                         Copyright (c) 2004 Peter Antoine
----------------------------------------------------------------------------
--- Version   Author Date        Changes
--- -------   ------ ----------  -------------------------------------------
--- 0.1       PA     03.07.2004  Initial revision
----------------------------------------------------------------------------


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.definitions.all;

entity tb_RandGen is


end entity tb_RandGen;


architecture behv of tb_RandGen is

    component RandomNumberGenerator
        port (  enable  : in    std_logic;
                clock   : in    std_logic;
                reset   : in    std_logic;
                seed    : in    std_logic_vector(data_width-1 downto 0);
                dstrobe : out   std_logic;
                result  : out   std_logic_vector(data_width-1 downto 0));
    end component RandomNumberGenerator;


    signal power_on         : std_logic := '1';

    signal enable           : std_logic := '0';
    signal running_enable   : std_logic := '0';
    signal enable_off       : std_logic := '1';
    signal clock            : std_logic;
    signal dstrobe          : std_logic;

    signal result           : std_logic_vector (data_width-1 downto 0);

    --- result file to test the randomness of the output
    subtype data_vector is bit_vector(data_width-1 downto 0);
    type bits_file is file of data_vector;
    file bitstream_file : bits_file open write_mode is "bitstream.log";

begin

    --- generate the clock
    clock <= '0' after 5 ns when (clock = '1') else '1' after 5 ns;

    --- reset the system.
    power_on <= '0' after 30 ns;

    --- genrate the enable
    enable_off <= '0' after 130 ns;

    process (running_enable,dstrobe)
    begin
        if (running_enable = '0') then
            running_enable <= '1' after 13 ns;

        elsif (dstrobe = '1') then
            running_enable <= '0' after 17 ns;
        end if;
    end process;

    enable <= (not enable_off) and running_enable;

    --- What we are testing
    RNG: RandomNumberGenerator port map (enable=>enable,clock=>clock,reset=>power_on,seed=>TEST_SEED,dstrobe=>dstrobe,result=>result);


    --- keep a log...

    process (dstrobe)
    begin
        -- problem why this does not seem to dump is that 02 and 03 are '1' and '0' in the
        -- the std_logic type. Will have to convert to bits to do this.
        --
        -- PPS: You can really dump real hex (binary) from VHDL, you need to do some coversion
        -- afterwards. I'll knock up a C prog to convert from bitvector to binary.

        if (dstrobe'event and dstrobe = '1') then
            write(bitstream_file,to_bitvector(result));
        end if;
    end process;

end architecture behv;

--- $Id: tb_randgen.vhd,v 1.4 2004/08/13 19:40:28 hardware Exp $
--- vi:nocin:sw=4 ts=4